Silicon Laboratories C8051F340 Uživatelský manuál Strana 94
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- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
C8051F340/1/2/3/4/5/6/7
94 Rev. 0.5
SFR Definition 9.11. EIE2: Extended Interrupt Enable 2
SFR Definition 9.12. EIP2: Extended Interrupt Priority 2
Bits7–2: UNUSED. Read = 000000b. Write = don’t care.
Bit1: ES1: Enable UART1 Interrupt.
This bit sets the masking of the UART1 interrupt.
0: Disable UART1 interrupt.
1: Enable UART1 interrupt.
Bit0: EVBUS: Enable VBUS Level Interrupt.
This bit sets the masking of the VBUS interrupt.
0: Disable all VBUS interrupts.
1: Enable interrupt requests generated by VBUS level sense.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - - - ES1 EVBUS 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xE7
Bits7–2: UNUSED. Read = 000000b. Write = don’t care.
Bit1: PS1: UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority level.
1: UART1 interrupts set to high priority level.
Bit0: PVBUS: VBUS Level Interrupt Priority Control.
This bit sets the priority of the VBUS interrupt.
0: VBUS interrupt set to low priority level.
1: VBUS interrupt set to high priority level.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - - - PS1 PVBUS 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xF7
- C8051F340/1/2/3/4/5/6/7 1
- Rev. 0.5 19 19
- 20 Rev. 0.5 20
- 1.1.1. Fully 8051 Compatible 21
- 1.1.2. Improved Throughput 21
- 1.1.3. Additional Features 21
- Microcontroller 22
- C8051F340/1/4/5 36
- Top View 36
- 5.3.1. Starting a Conversion 45
- 5.3.2. Tracking Modes 46
- 9.2.1. Program Memory 79
- 9.2.2. Data Memory 80
- 9.2.5. Stack 80
- 9.2.7. Register Descriptions 85
- 9.3.2. External Interrupts 87
- 9.3.3. Interrupt Priorities 88
- 9.3.4. Interrupt Latency 88
- 9.4.1. Idle Mode 96
- 9.4.2. Stop Mode 96
- 12.1.2. Flash Erase Procedure 109
- 12.1.3. Flash Write Procedure 110
- 13.1.1. 16-Bit MOVX Example 117
- 13.1.2. 8-Bit MOVX Example 117
- 13.6.1. Internal XRAM Only 124
- 13.6.4. External Only 125
- 13.7.1. Non-multiplexed Mode 127
- 13.7.2. Multiplexed Mode 130
- 14.3.3. External RC Example 140
- 14.5.2. USB Clock Selection 143
- 16.5.1. FIFO Split Mode 171
- 16.5.2. FIFO Double Buffering 172
- 16.5.1. FIFO Access 172
- 17.3.1. Arbitration 195
- 17.3.2. Clock Low Extension 196
- 17.3.3. SCL Low Timeout 196
- 17.4.3. Data Register 204
- 17.5.2. Master Receiver Mode 206
- 17.5.3. Slave Receiver Mode 207
- 18.2.1. 8-Bit UART 213
- 18.2.2. 9-Bit UART 214
- 19.3.1. Data Transmission 222
- 19.3.2. Data Reception 222
- 20.1.3. Serial Clock (SCK) 230
- 20.1.4. Slave Select (NSS) 230
- 266 Rev. 0.5 266
- Rev. 0.5 267 267
- 268 Rev. 0.5 268
- 22.2.4. Frequency Output Mode 269
- 270 Rev. 0.5 270
- Rev. 0.5 271 271
- WDT updates are performed 272
- PCA clocks) by 272
- 22.3.2. Watchdog Timer Usage 273
- 23.2. C2 Pin Sharing 281
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